Semiconductor device

ABSTRACT

A semiconductor device including a first fin field effect transistor and a second fin field effect transistor is provided. The first fin field effect transistor includes a first semiconductor channel, a first gate overlapped with the first semiconductor channel, a first dielectric layer disposed between the first semiconductor channel and the first gate, and a pair of first spacers disposed on sidewalls of the first gate. The second fin field effect transistor includes a second semiconductor channel, a second gate overlapped with the second semiconductor channel, a second dielectric layer disposed between the second semiconductor channel and the second gate, and a pair of second spacers. The second dielectric layer further extends between the second gate and the pair of second spacers, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. application Ser. No. 14/968,916, filed on Dec. 15, 2015. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

As the semiconductor devices keeps scaling down in size, three-dimensional multi-gate structures, such as the fin-type field effect transistors (FinFETs), have been developed to replace planar Complementary Metal Oxide Semiconductor (CMOS) devices. A structural feature of the FinFET is the silicon-based fin that extends upright from the surface of the substrate, and the gate wrapping around the conducting channel that is formed by the fin further provides a better electrical control over the channel.

For the gate replacement process of the FinFET with short channel (i.e. channel length smaller than 50 nm), a portion of oxide layer covering the silicon-based fin is needed to be over-etched such that process window of the sequential depositions for high-k dielectric layer and gate is better. However, high etching amount of oxide layer induces leakage path and extrusion path for metal gate.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flow chart illustrating a method for fabricating a semiconductor device in accordance with some embodiments.

FIGS. 2A-2L are perspective views of a method for fabricating a semiconductor device in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

The embodiments of the present disclosure describe the exemplary fabricating process of a semiconductor device which comprises at least one long channel FinFET and at least one short channel FinFET. The semiconductor device may be formed on bulk silicon substrates in certain embodiments of the present disclosure. Still, the semiconductor device may be formed on a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate as alternatives. Also, in accordance with the embodiments, the silicon substrate may include other conductive layers or other semiconductor elements, such as transistors, diodes or the like. The embodiments are not limited in this context.

Referring to FIG. 1, illustrated is a flow chart illustrating a method for fabricating a semiconductor device in accordance with some embodiments of the present disclosure. The fabricating method at least includes steps S10, step S12, step S14, step S16, step S18, step S20, step 22, step 24 and step S26. First, in step S10, a substrate is provided, and the substrate is then patterned to form a plurality of trenches and a plurality semiconductor fins between the trenches. In step S12, a plurality of insulators are formed in the trenches. The insulators are shallow trench isolation (STI) structures for insulating semiconductor fins, for example. In step S14, a first dielectric layer is formed to cover the semiconductor fins and the insulators. In step S16, at least one first dummy gate strip and at least one second dummy gate strip are formed on the first dielectric layer, wherein lengthwise directions of the first and second dummy gate strips are different from a lengthwise direction of the semiconductor fins, and a width of the first dummy gate strip is smaller than a width of the second dummy gate strip. The first dummy gate strip and the second dummy gate strip are conductive strips, such as poly-silicon strips. In step S18, a pair of first spacers and a pair of second spacers are formed on sidewalls of the first and second dummy gate strips respectively. In step S20, the first dummy gate strip is removed to form a first cavity. In step S22, the second dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the second spacers, a portion of the semiconductor fins and portions of the insulators are exposed so as to form a second cavity. In step S24, a second dielectric layer is conformally formed in the second cavity to cover the sidewalls of the second spacers, the exposed portion of the semiconductor fins and the exposed portions of the insulators, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. The second dielectric layer is formed by atomic layer deposition (ALD), chemical vapor deposition (CVD) or physical vapor deposition (PVD), for example. In step S26, a first gate is formed in the first cavity and a second gate is formed on the second dielectric layer and in the second cavity. As illustrated in FIG. 1, removal of the first dummy gate strip is performed before removal of the second dummy gate strip. However, removal sequence of the first dummy gate strip (step S20) and the second dummy gate strip (step S22) is not limited in the present disclosure.

FIG. 2A is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step 10 in FIG. 1 and as shown in FIG. 2A, a substrate 200 is provided. In one embodiment, the substrate 200 comprises a crystalline silicon substrate (e.g., wafer). The substrate 200 may comprise various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped regions may be doped with p-type and/or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF₂; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for an n-type FinFET, a p-type FinFET or the combination thereof. In some alternative embodiments, the substrate 200 may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

In one embodiment, a pad layer 202 a and a mask layer 202 b are sequentially formed on the substrate 200. The pad layer 202 a may be a silicon oxide thin film formed, for example, by thermal oxidation process. The pad layer 202 a may act as an adhesion layer between the substrate 200 and mask layer 202 b. The pad layer 202 a may also act as an etch stop layer for etching the mask layer 202 b. In at least one embodiment, the mask layer 202 b is a silicon nitride layer formed, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer 202 b is used as a hard mask during subsequent photolithography processes. Then, a patterned photoresist layer 204 having a predetermined pattern is formed on the mask layer 202 b.

FIG. 2B is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S10 in FIG. 1 and as shown in FIGS. 2A-2B, the mask layer 202 b and the pad layer 202 a which are not covered by the patterned photoresist layer 204 are sequentially etched to form a patterned mask layer 202 b′ and a patterned pad layer 202 a′ so as to expose underlying substrate 200. By using the patterned mask layer 202 b′, the patterned pad layer 202 a′ and the patterned photoresist layer 204 as a mask, portions of the substrate 200 are exposed and etched to form trenches 206 and semiconductor fins 208. After the substrate 200 is patterned, the semiconductor fins 208 are covered by the patterned mask layer 202 b′, the patterned pad layer 202 a′ and the patterned photoresist layer 204. Two adjacent trenches 206 are spaced apart by a spacing S. For example, the spacing S between trenches 206 may be smaller than about 30 nm. In other words, two adjacent trenches 206 are spaced apart by a corresponding semiconductor fin 208.

The height of the semiconductor fins 208 and the depth of the trench 206 range from about 5 nm to about 500 nm. After the trenches 206 and the semiconductor fins 208 are formed, the patterned photoresist layer 204 is then removed. In one embodiment, a cleaning process may be performed to remove a native oxide of the semiconductor substrate 200 a and the semiconductor fins 208. The cleaning process may be performed using diluted hydrofluoric (DHF) acid or other suitable cleaning solutions.

FIG. 2C is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S12 in FIG. 1 and as shown in FIGS. 2B-2C, an insulating material 210 are formed over the substrate 200 a to cover the semiconductor fins 208 and fill up the trenches 206. In addition to the semiconductor fins 208, the insulating material 210 further covers the patterned pad layer 202 a′ and the patterned mask layer 202 b′. The insulating material 210 may include silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-K dielectric material. The insulating material 210 may be formed by high-density-plasma chemical vapor deposition (HDP-CVD), sub-atmospheric CVD (SACVD) or by spin-on.

FIG. 2D is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S12 in FIG. 1 and as shown in FIGS. 2C-2D, a chemical mechanical polish process is, for example, performed to remove a portion of the insulating material 210, the patterned mask layer 202 b′ and the patterned pad layer 202 a′ until the semiconductor fins 208 are exposed. As shown in FIG. 2D, after the insulating material 210 is polished, top surfaces of the polished insulating material 210 is substantially coplanar with top surface T2 of the semiconductor fins.

FIG. 2E is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S12 in FIG. 1 and as shown in FIGS. 2D-2E, the polished insulating material 210 filled in the trenches 206 is partially removed by an etching process such that insulators 210 a are formed on the substrate 200 a and each insulator 210 a is located between two adjacent semiconductor fins 208. In one embodiment, the etching process may be a wet etching process with hydrofluoric acid (HF) or a dry etching process. The top surfaces T1 of the insulators 210 a are lower than the top surfaces T2 of the semiconductor fins 208. In other words, the semiconductor fins 208 protrude from the top surfaces T1 of the insulators 210 a and sidewalls SW of the semiconductor fins 208 are thus exposed. The height difference between the top surfaces T2 of the fins 208 and the top surfaces T1 of the insulators 210 a is H, and the height difference H ranges from about 15 nm to about 50 nm.

FIG. 2F is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S14 in FIG. 1 and as shown in FIGS. 2E-2F, after the insulators 210 a are formed, a first dielectric layer 212 is formed to conformally cover the top surface T1 of the insulators 210 a, the top surfaces T2 of the semiconductor fins 208 and the sidewall SW of the semiconductor fins 208. In one embodiment, the first dielectric layer 212 may include silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectrics. High-k dielectrics comprise metal oxides. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or mixtures thereof. In one embodiment, the first dielectric layer 212 is a high-k dielectric layer with a thickness in the range of about 0.2 nm to 5 nm. The first dielectric layer 212 may be formed by a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation or UV-ozone oxidation. The first dielectric layer 212 is thin enough and has good quality to serve as a gate dielectric layer in short channel FinFETs.

FIG. 2G is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S16 in FIG. 1 and as shown in FIGS. 2F-2G, at least one first dummy gate strip 214 a and at least one second dummy gate strip 214 b are formed on the first dielectric layer 212, wherein lengthwise directions D1 of the first and second dummy gate strips 214 a, 214 b are different from a lengthwise direction D2 of the semiconductor fins 208. Along the lengthwise direction D1, a first width W1 of the first dummy gate strip 214 a is smaller than a second width W2 of the second dummy gate strip 214 b. The lengthwise directions D1 of the first and second dummy gate strips 214 a, 214 b are perpendicular to the lengthwise direction D2 of the semiconductor fins 208, for example. The number of the first and second dummy gate strips 214 a, 214 b shown in FIG. 2G is merely for illustration, in some alternative embodiments, two or more first and second dummy gate strips 214 a, 214 b may be formed in accordance with actual design requirements. The first and second dummy gate strips 214 a, 214 b include a silicon-containing material, such as poly-silicon, amorphous silicon or a combination thereof. In one embodiment, the first width W1 of the first dummy gate strip 210 a ranges from 5 nm to 50 nm and the second width W2 of the second dummy gate strip 210 b is greater than 55 nm.

In Step S18 in FIG. 1 and as shown in FIG. 2G, after the first and second dummy gate strips 214 a, 214 b are formed, a pair of first spacers 216 a and a pair of second spacers 216 b are formed on sidewalls of the first and second dummy gate strips 214 a, 214 b respectively. As shown in FIG. 2H, the first spacers 216 a are formed on the first dielectric layer 212 and extend along the sidewalls of the first dummy gate strip 214 a while the second spacers 216 b are formed on the first dielectric layer 212 and extend along the sidewalls of the second dummy gate strip 214 b. The first and second spacers 216 a, 216 b are formed of dielectric materials, such as silicon nitride or SiCON. The first and second spacers 216 a, 216 b may include a single layer or multilayer structure. Since the pair of first spacers 216 a are spaced apart by the first dummy gate strip 214 a, a first gap G1 between the pair of first spacer 216 a substantially equals to the first width W1 of the first dummy gate strip 214 a. Similarly, a second gap G2 between the pair of second spacer 216 b substantially equals to the second width W2 of the second dummy gate strip 214 b.

FIG. 2H is a perspective view of the semiconductor device at one of various stages of the manufacturing method. As shown in FIG. 2H, interlayer dielectric layers 218 are formed to cover the first dielectric layer 212. Top surfaces of the interlayer dielectric layers 218 are substantially co-planar with top surfaces of the first dummy gate strip 214 a and the second dummy gate strip 214 b. In some embodiments, before the interlayer dielectric layers 218 are formed, some processes (e.g. patterning process of first dielectric layer 212, fin recessing process, strained source/drain epitaxial process on the semiconductor fins, silicidation process and so on) may be performed in advance. Details of the aforesaid processes are omitted.

FIG. 2I-2J are perspective views of the semiconductor device at various stages of the manufacturing method. In Steps S20, S22 in FIG. 1 and as shown in FIGS. 2H-2J, the first dummy gate strip 214 a and the second dummy gate strip 214 b are removed. In one embodiment, the first dummy gate strip 214 a and the second dummy gate strip 214 b are removed, for example, by an etching process. Through properly selecting of etchant, the first dummy gate strip 214 a and the second dummy gate strip 214 b are removed without damaging the interlayer dielectric layers 218, the first dielectric layer 212, the first spacers 216 a and the second spacer 216 b significantly. After the first dummy gate strip 214 a is removed, a first cavity C1 between the pair of first spacers 216 a is formed and a portion of first dielectric layer 212 is thus exposed. A portion of the semiconductor fin 208 (shown in the right portion of FIG. 2J) corresponding to the first cavity C1 is still covered by the first dielectric layer 212.

As shown in FIG. 2J, a portion of the first dielectric layer 212 and portions of the insulators 210 a located under the second dummy gate strip 214 b are further removed until sidewalls of the second spacers 216 b, a portion of the semiconductor fins 208 and portions of the insulators 210 a are exposed so as to form a second cavity C2. During the formation of the second cavity C2, the first dielectric layer 212 exposed by the first cavity C1 is, for example, well protected from being removed. In one embodiment, the first dielectric layer 212 exposed by the first cavity C1 may be protected and covered by a photoresist layer from being removed.

During the formation of the second cavity C2, the first dielectric layer 212 is etched-off and is over-etched slightly. In some alternative embodiments, during the formation of the second cavity C2, the insulators 210 a may function as etching stop layers so as to control the profile of the second cavity C2. After the second cavity C2 is formed, a portion of the semiconductor fin 208 (shown in the left portion of FIG. 2J) corresponding to the second cavity C2 is exposed. It is noted that, along the lengthwise direction D2 of the semiconductor fins 208, the portion of the semiconductor fin 208 (shown in the left portion of FIG. 2J) corresponding to the second cavity C2 has greater dimension while the portion of the semiconductor fin 208 (shown in the right portion of FIG. 2J) corresponding to the first cavity C1 has smaller dimension.

FIG. 2K is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In Step S24 in FIG. 1 and as shown in FIGS. 2J-2K, after the second cavity C2 is formed, a second dielectric layer 220 is conformally formed in the second cavity C2 so as to cover the sidewalls of the second spacers 216 b, the exposed portion of the semiconductor fin 208 and the exposed portions of the insulators 210 a, wherein a thickness of the first dielectric layer 212 is smaller than a thickness of the second dielectric layer 220. The second dielectric layer 220 formed in the second cavity C2 has a continuous pattern. In one embodiment, the second dielectric layer 220 may include silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectrics. High-k dielectrics comprise metal oxides. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or mixtures thereof. In one embodiment, the second dielectric layer 220 is a high-k dielectric layer with a thickness in the range of about 5 nm to 50 nm. The second dielectric layer 220 may be formed by a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD) or physical vapor deposition (PVD). The second dielectric layer 220 is thicker than the first dielectric layer 212 and is suitable for serving as a gate dielectric layer in long channel FinFETs.

As shown in FIGS. 2K-2L, a first gate 222 a is formed in the first cavity C1 and a second gate 222 b is formed on the second dielectric layer 220 and in the second cavity C2. In some embodiments, the first gate 222 a and the second gate 222 b may comprise a single layer or multi-layered structure. In some embodiments, the first gate 222 a and the second gate 222 b may comprise metal, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, other conductive materials with a work function compatible with the substrate material, or combinations thereof. In some embodiments, a thickness of the first gate 222 a and the second gate 222 b is, for example, in the range of about 30 nm to about 60 nm. The first gate 222 a and the second gate 222 b may be formed by a suitable process such as ALD, CVD, PVD, plating, or combinations thereof.

In one embodiment, the width W3 of the first gate 222 a ranges from 5 nm to 50 nm and the width W4 of the second gate 222 b is greater than 50 nm. The portion of the semiconductor fin 208 that is overlapped with and covered by the first gate 222 a serves as a channel of a short channel FinFET; and the portion of the semiconductor fin 208 that is overlapped with and covered by the second gate 222 b serves as a channel of along channel FinFET.

As shown in FIG. 2G and FIG. 2L, the width W3 of the first gate 222 a, the width W1 of the first dummy gate strip 214 a and the first gap G1 between the pair of first spacer 216 a are substantially equal (i.e. W3=W1=G1). The width W4 of the second gate 222 b is smaller than the width W2 of the second dummy gate strip 214 b and the second gap G2 between the pair of second spacer 216 b (i.e. W4<W2=G2).

In the short channel FinFET (shown in the right portion of FIG. 2L), the thinner first dielectric layer 212 is formed to serve as a gate dielectric layer; in the long channel FinFET (shown in the left portion of FIG. 2L), the thinner first dielectric layer 212 is removed and replaced by the thicker second dielectric layer 220. Since the second dielectric layer 220 is conformally formed in the second cavity C2 and has a continuous pattern, leakage path and extrusion path for the second gate 222 b can be prevented. Accordingly, process window of gate replacement process is enlarged. Therefore, yield and reliability of the semiconductor device are enhanced.

In accordance with some embodiments of the present disclosure, a semiconductor device including a substrate, a plurality of insulators, a first dielectric layer, a pair of first spacers, a first gate, a pair of second spacers, a second dielectric layer and a second gate is provided. The substrate includes a plurality of insulators and a semiconductor fin between the insulators. The first dielectric layer partially covers the semiconductor fin and the insulators, and the first dielectric layer reveals a portion of the semiconductor fin and portions of the insulators. The pair of first spacers are disposed on the first dielectric layer. The first gate is disposed on the first dielectric layer and between the pair of first spacers. The pair of second spacers are disposed on the first dielectric layer. The second dielectric layer is disposed between the pair of second spacers. The second dielectric layer conformally covers sidewalls of the second spacers and the portion of the semiconductor fin revealed by the first dielectric layer. The first dielectric layer is thinner than the second dielectric layer. The second gate is disposed on the second dielectric layer and between the second spacers, wherein a width of the first gate is smaller than a width of the second gate.

In accordance with alternative embodiments of the present disclosure, a semiconductor device including a first fin field effect transistor and a second fin field effect transistor is provided. The first fin field effect transistor includes a first semiconductor channel, a first gate overlapped with the first semiconductor channel, a first dielectric layer disposed between the first semiconductor channel and the first gate, and a pair of first spacers disposed on sidewalls of the first gate. The second fin field effect transistor includes a second semiconductor channel, a second gate overlapped with the second semiconductor channel, a second dielectric layer disposed between the second semiconductor channel and the second gate, and a pair of second spacers. The second dielectric layer further extends between the second gate and the pair of second spacers, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.

In accordance with yet alternative embodiments of the present disclosure, a semiconductor device including a semiconductor fin, a first gate, a first dielectric layer, a pair of first spacers, a second dielectric layer, a second gate and a pair of second spacers is provided. The semiconductor fin includes a first channel portion and a second channel portion. The first gate is overlapped with the first channel portion of the semiconductor fin. The first dielectric layer covers the first channel portion of the semiconductor fin, wherein the first dielectric layer is between the first gate and the first channel portion of the semiconductor fin. The pair of first spacers are disposed on the first dielectric layer and cover sidewalls of the first gate. The second dielectric layer covers the second channel portion of the semiconductor fin, the second channel portion is uncovered by the first dielectric layer, and the first dielectric layer is thinner than the second dielectric layer. The second gate is disposed on the second dielectric layer and overlapped with the second channel portion of the semiconductor fin, and a width of the first gate is smaller than that of the second gate. The pair of second spacers are disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the pair of second spacers to space apart the second gate from the pair of second spacers.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A semiconductor device, comprising: a substrate comprising a plurality of insulators and a semiconductor fin between the insulators; a first dielectric layer partially covering the semiconductor fin and the insulators, the first dielectric layer revealing a portion of the semiconductor fin and portions of the insulators; a pair of first spacers disposed on the first dielectric layer; a first gate disposed on the first dielectric layer and between the pair of first spacers; a pair of second spacers disposed on the first dielectric layer; a second dielectric layer disposed between the pair of second spacers, wherein the second dielectric layer conformally covers sidewalls of the second spacers and the portion of the semiconductor fin revealed by the first dielectric layer, and the first dielectric layer is thinner than the second dielectric layer; and a second gate disposed on the second dielectric layer and between the second spacers, wherein a width of the first gate is smaller than a width of the second gate.
 2. The semiconductor device of claim 1, wherein a thickness of the first dielectric layer ranges from 0.2 nm to 5 nm and a thickness of the second dielectric layer ranges from 5 nm to 50 nm.
 3. The semiconductor device of claim 1, wherein the width of the first gate ranges from 5 nm to 50 nm and the width of the second gate is greater than 50 nm.
 4. The semiconductor device of claim 1, wherein the second dielectric layer extends along the sidewalls of the second spacers and is between the second gate and the pair of second spacers.
 5. The semiconductor device of claim 1, wherein the width of the second gate is smaller than a gap between the pair of second spacers.
 6. The semiconductor device of claim 1, wherein the width of the first gate is substantially equal to a gap between the pair of first spacers.
 7. A semiconductor device, comprising: a first fin field effect transistor comprising a first semiconductor channel, a first gate overlapped with the first semiconductor channel, a first dielectric layer disposed between the first semiconductor channel and the first gate, and a pair of first spacers disposed on sidewalls of the first gate; and a second fin field effect transistor comprising a second semiconductor channel, a second gate overlapped with the second semiconductor channel, a second dielectric layer disposed between the second semiconductor channel and the second gate, and a pair of second spacers, wherein the second dielectric layer further extends between the second gate and the pair of second spacers, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.
 8. The semiconductor device of claim 7, wherein a thickness of the first dielectric layer ranges from 0.2 nm to 5 nm and a thickness of the second dielectric layer ranges from 5 nm to 50 nm.
 9. The semiconductor device of claim 7, wherein the width of the first gate ranges from 5 nm to 50 nm and the width of the second gate is greater than 50 nm.
 10. The semiconductor device of claim 7, wherein a channel length of the first semiconductor channel ranges from 5 nm to 50 nm and a channel length of the second semiconductor channel is greater than 50 nm.
 11. The semiconductor device of claim 7, wherein a channel length of the first semiconductor channel is smaller than that of the second semiconductor channel.
 12. The semiconductor device of claim 7, wherein the width of the first gate is substantially equal to a gap between the pair of first spacers.
 13. The semiconductor device of claim 7, wherein the width of the second gate is smaller than a gap between the pair of second spacers.
 14. A semiconductor device, comprising: a semiconductor fin comprising a first channel portion and a second channel portion; a first gate overlapped with the first channel portion of the semiconductor fin; a first dielectric layer covering the first channel portion of the semiconductor fin, the first dielectric layer being between the first gate and the first channel portion of the semiconductor fin; a pair of first spacers disposed on the first dielectric layer and covering sidewalls of the first gate; a second dielectric layer covering the second channel portion of the semiconductor fin, the second channel portion being uncovered by the first dielectric layer, and the first dielectric layer being thinner than the second dielectric layer; a second gate disposed on the second dielectric layer and overlapped with the second channel portion of the semiconductor fin, a width of the first gate being smaller than that of the second gate; and a pair of second spacers disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the pair of second spacers to space apart the second gate from the pair of second spacers.
 15. The semiconductor device of claim 14, wherein a thickness of the first dielectric layer ranges from 0.2 nm to 5 nm and a thickness of the second dielectric layer ranges from 5 nm to 50 nm.
 16. The semiconductor device of claim 14, wherein the width of the first gate ranges from 5 nm to 50 nm and the width of the second gate is greater than 50 nm.
 17. The semiconductor device of claim 14, wherein a channel length of the first channel portion ranges from 5 nm to 50 nm and a channel length of the second channel portion is greater than 50 nm.
 18. The semiconductor device of claim 14, wherein a channel length of the first channel portion is smaller than that of the second channel portion.
 19. The semiconductor device of claim 14, wherein the width of the first gate is substantially equal to a gap between the pair of first spacers.
 20. The semiconductor device of claim 14, wherein the width of the second gate is smaller than a gap between the pair of second spacers. 